1 radiation hardened quad differential line receiver hs-26c32rh, hs-26c32eh the intersil hs-26c32rh, hs-26c 32eh are differential line receivers designed for digital da ta transmission over balanced lines and meets the requiremen ts of eia standard rs-422. radiation hardened cmos processing assures low power consumption, high speed, and re liable operation in the most severe radiation environments. the hs-26c32rh, hs-26c32eh have an input sensitivity typically of 200mv over the common mode input voltage range of 7v. the receivers are also equipped with input fail safe circuitry, which causes the outputs to go to a logic ?1? when the inputs are open. enable and disable functions are common to all four receivers. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbers listed in the ?ordering information? table must be used when ordering. detailed electrical specifications for these devices are contained in smd 5962-95689 . a ?hot-link? is provided on our homepage for downloading features ? electrically screened to smd # 5962-95689 ? qml qualified per mil-prf-38535 requirements ? 1.2 micron radiation hardened cmos - total dose . . . . . . . . . . . . . . . . . . . . . . . . 300 krad(si) (max) ?latch-up free ? eia rs-422 compatible inputs ? cmos compatible outputs ? input fail safe circuitry ? high impedance inputs when disabled or powered down ? low power dissipation 138mw standby (max) ?single 5v supply ? full -55c to +125c military temperature range applications ? line receiver for mil-std-1553 serial data bus ordering information ordering number (note 1) internal mkt. number part marking temp. range (c) package (pb-free) pkg. dwg. # 5962f9568901qec hs1-26c32rh-8 q 5962f95 68901qec -55 to +125 16 ld sbdip d16.3 5962f9568901qxc hs9-26c32rh-8 q 5962f95 68901qxc -55 to +125 16 ld flatpack k16.a 5962f9568901v9a hs0-26c32rh-q -55 to +125 die hs0-26c32rh/sample hs0-26c32rh/sample -55 to +125 die 5962f9568901vec hs1-26c32rh-q q 5962f95 68901vec -55 to +125 16 ld sbdip d16.3 5962f9568901vxc hs9-26c32rh-q q 5962f95 68901vxc -55 to +125 16 ld flatpack k16.a hs1-26c32rh/proto hs1-26c32rh/proto hs1- 26c 32rh /proto -55 to +125 16 ld sbdip d16.3 hs9-26c32rh/proto hs9-26c32rh/proto hs9- 26c32rh /proto -55 to +125 16 ld flatpack k16.a 5962f9568903vec hs1-26c32eh-q q 5962f95 68903vec -55 to +125 16 ld sbdip d16.3 5962f9568903vxc hs9-26c32eh-q q 5962f95 68903vxc -55 to +125 16 ld flatpack k16.a 5962f9568903v9a hs0-26c32eh-q q 5962f95 68903v9a -55 to +125 die 5962f9568901vyc hs9g-26c32rh-q (note 2) q 5962f95 68901vyc -55 to +125 16 ld flatpack k16.a hs9g-26c32rh/proto hs9g-26c32rh/proto (note 2) hs9g-26c32rh/proto -55 to +125 16 ld flatpack k16.a notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. 2. the lid of these packages are connect ed to the ground pin of the device. may 28, 2013 fn3402.5 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2012, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
hs-26c32rh, hs-26c32eh 2 fn3402.5 may 28, 2013 logic diagram propagation delay timing diagram three-state low timing diagram enable enable aout bout cout din dout din cin cin bin bin ain ain +- +- +- +- pin configurations hs1-26c32rh, hs1-26c32eh (16 ld sbdip) mil-std-1835: cdip2-t16 top view hs9-26c32rh, hs9-26c32eh (16 ld flatpack) mil-std-1835: cdfp4-f16 top view 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 ain ain aout enable cout cin gnd cin vdd bin bout enable dout din din bin ain ain aout enable cout cin cin gnd 2 3 4 5 6 7 8 116 15 14 13 12 11 10 9 vdd bin bin bout enable dout din din input output -v in +v in = 0v v oh v ol 0v -2.5v +2.5v v s = 50% t plh t phl v s input v ih v ss t pzl t plz output v oz v ol v t v w
hs-26c32rh, hs-26c32eh 3 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn3402.5 may 28, 2013 for additional products, see www.intersil.com/en/products.html propagation delay load circuit three-state high timing diagrams three-state low load circuit three-state high load circuit table 1. three-state low voltage levels parameter hs-26c32rh hs-26c32eh units v dd 4.50 v v ih 4.50 v v s 2.25 v v t 50 % v w v ol + 0.5 v gnd 0 v dut test c l r l point c l = 50pf r l = 1000 v s input t pzh t phz output v oh v oz v t v w v ih v ss table 2. three-state high voltage levels parameter hs-26c32rh hs-26c32eh units v dd 4.50 v v ih 4.50 v v s 2.25 v v t 50 % v w v oh - 0.5 v gnd 0 v dut test c l r l point c l = 50pf r l = 1000 v dd dut test c l r l point c l = 50pf r l = 1000
hs-26c32rh, hs-26c32eh 4 fn3402.5 may 28, 2013 die characteristics die dimensions: 78 mils x 123 mils (1970m x 3120m) interface materials: glassivation: type: sio 2 thickness: 10k ? 1k ? top metallization: m1: mo/tiw thickness: 5800 ? m2: al/si/cu thickness: 5800 ? worst case current density: <2.0 x 10 5 a/cm 2 bond pad size: 110m x 100m metallization mask layout hs-26c32rh, hs-26c32eh ain v dd bin ain (2) a out (3) enab (4) c out (5) c in (6) (8) (9) (14) b in (13) b out (12) enab (11) d out (10) d in (1) (16) (15) (7) cin gnd din
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